James McCartan

James joined the CDT in September 2017, having previously completed an MSci in Physics at Queen's University Belfast.

In Semester 1 of 2017-18 James completed a short exploratory research project at the University of Glasgow in Fibre-optic interface for waveguide circuits, supervised by Professor Robert Hadfield. In Semester 2 of 2017-18, he conducted a practical research project at Queen's University Belfast supervised by Dr Amit Kumar, Characterising nanoscale thermal transport across functional interfaces using scanning Thermal microscopy.

 

CDT PhD Project

MAKING AND CHARACTERISING ATOMIC SCALE 1D P-N JUNCTIONS FOR NANOSCALE LOGIC GATES

Supervisors:

Professor Marty Gregg, Queen's University Belfast

Dr Ian MacLaren, University of Glasgow

There are a growing number of multiferroic materials (systems which are both magnetic and ferroelectric) which have conducting domain walls. While the details of transport remain uncertain, it seems clear that strong electric fields, associated with discontinuities in electrical polarisation, attract free carriers, which can then travel along the walls with mobilities comparable to single crystal silicon. Interestingly, the nature and sign of the polar discontinuity can be controlled in multiferroics using magnetic fields, determining whether aggregated carriers are n (at head-to-head polar walls) or p-type (at tail-to-tail polar walls). Since both n and p-type walls can be made, domain wall intersection points can be engineered to form 1D p-n junctions, which display obvious diode-like characteristics.

Controlled arrangements of diodes can in principle, allow logic gates to be designed and the eventual aim of this PhD project will be to make, investigate and test such domain-wall based logic gate patterns. The notion of atomic scale 1D p-n junctions at domain wall intersections is highly novel (QUB has been the first to show this), but to use such 1D junctions in the formation of entire domain wall logic gates is a new paradigm. Given that domain walls are innately mobile and can be both created and destroyed, demonstration of in-wall logic gates automatically suggests agile, transient or ephemeral data processors.

The first stage will be to make and investigate 1D p-n junctions at domain wall intersection points, using a new kind of scanning probe microscopy at QUB to verify the carrier types. Nanoscale electrical testing will then be used to tease out the detailed characteristics of the diodes and this will be coupled with advanced electron microscopy, in QUB (using the new FIBs and the Talos microscope) and in Glasgow, to examine atomic scale structure and the band structures throughout the p-n junction device. Advanced in-situ TEM, characterising the domain wall diodes in operation, will be performed in Limerick using their Titan system with in-situ bias. Methods to control the arrangement of several junctions in parallel to create logic gates will then be investigated, with the project hopefully culminating in the successful testing and demonstration of in-domain wall logic. The use of multiferroics is inherent to the study and agile behaviour associated with exposure to magnetic fields will also be investigated.